Size reduction of metal-oxide-semiconductor field-effect transistors (MOSFETs), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. To further enhance transistor performance, MOSFET devices have been fabricated using strained channel regions located in portions of a semiconductor substrate. Strained channel regions allow enhanced carrier mobility to be realized, thereby resulting in increased performance when used for n-channel (NMOSFET) or for p-channel (PMOSFET) devices. Generally, it is desirable to induce a tensile strain in the n-channel of an NMOSFET transistor in the source-to-drain direction to increase electron mobility and to induce a compressive strain in the p-channel of a PMOSFET transistor in the source-to-drain direction to increase hole mobility. There are several existing approaches of introducing strain in the transistor channel region.
In one approach, semiconductor alloy layers, such as silicon-germanium or silicon-germanium-carbon, are formed below an overlying thin semiconductor layer, wherein the semiconductor alloy layer has a different lattice structure than the overlying semiconductor layer. The difference in the lattice structure imparts strain in the overlying semiconductor layer to increase carrier mobility.
This approach, however, can be difficult to process in addition to presenting junction leakage concerns as a result of the blanket semiconductor alloy layer. The epitaxial growth of the semiconductor alloy layer, such as a silicon-germanium layer, can be costly and difficult to accurately control the level of germanium in the epitaxially grown semiconductor alloy layer. In addition, the presence of a blanket semiconductor alloy layer allows an unwanted interface between the source/drain regions to exist, possibly introducing junction leakage.
In another approach, strain in the channel is introduced after the transistor is formed. In this approach, a high-stress film is formed over a completed transistor structure formed in a silicon substrate. The high-stress film or stressor exerts significant influence on the channel, modifying the silicon lattice spacing in the channel region, and thus introducing strain in the channel region. In this case, the stressor is placed above the completed transistor structure. The device performance is obtained by increasing the stress or thickness of the high-stress film.
The amount of stress that may be applied, however, is limited. For example, the amount of stress that may be applied by a high-stress film is limited by, among other things, subsequent gap-fill capabilities and the etching window. Accordingly, there is a need for an efficient and cost-effective method to induce additional strain such that the performance characteristics of transistors are enhanced.